PATMOS 2019 Technical Program Rhodes,
Greece, 1-3rd July 2019
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Monday, July 1, 2019 |
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| 7:30 – 8:30 | Registration | |
| 8:30 – 9:45 | FEDFRO Opening Session | |
| 8:30 – 8:45 | Welcome Message | |
| 8:45 – 9:30 |
FEDFRO Keynote Talk “The EPI Processor and its Robustness Requirements”, Yingchih Yang, Lead Architect for the European Processor Initiative (EPI) project Abstract: The European Processor Initiative (EPI) represents the ambition of Europe in the High Performance Computing (HPC) field. It aims to develop critical technologies and generate key components for next generation HPC systems with primary focus on the EPI high-performance low-energy-consumption processor. In this talk we will present the project and vision of the team, and the robustness challenges of the EPI processor. |
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| 9:45-10:00 |
Break |
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| 10:00 -10:15 |
PATMOS Opening Session |
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| 10:15 – 11:15 | Session 1. Timing analysis and optimization Session chair: V. Paliouras S1.1 “The Involution Tool for Accurate Digital Timing and Power Analysis”, D. Öhlinger, J. Maier, M. Függer and U. Schmid S1.2 “Graph-Based STA for Asynchronous Controllers”, N. Xiromeritis, S. Simoglou, C. Sotiriou and N. Sketopoulos S1.3 “Multi-Armed Bandits for Autonomous Timing-driven Design Optimization”, A. Stefanidis, D. Mangiras, C. Nicopoulos and G. Dimitrakopoulos |
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| 11:15 – 12:15 | Poster Session A & Coffee break Session chair: G. Theodoridis A1 “UVM-based Verification of a Digital PLL Using SystemVerilog”, N. Georgoulopoulos and A. Hatzopoulos A2 “Investigating the Influence of Adiabatic Load on 4-phase Adiabatic System Implementation for Energy-Constraint Cryptographic Computations”, H. Singh Raghav and I. Kale A3 “A High-Performance Neuron for Artificial Neural Network based on Izhikevich model” M. Sapounaki and A. Kakarountas A4 “Implementing VESA Display Stream Compression Encoder in FPGAs”, N. Kefalas and G. Theodoridis A5 “FPGA-based Framework for Design Exploration of Ring-based Software-Managed Cache-Coherency”, G. Kornaros and O. Tomoutzoglou A6 “RISC-V Extensions for Bit Manipulation Instructions”, B. Koppelmann, P. Adelt, W. Mueller and C. Scheytt |
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| 12:15 – 13:15 | Session 2. When temperature and power matter
Session chair: O. Koufopavlou S2.1 “A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems”, M. Noltsis, N. Zambelis, F. Catthoor and D. Soudris. S2.2 “Temperature-aware writing architecture for multilevel memristive cells”, A. de Gracia and M. Lopez-Vallejo S2.3 “Adaptive Transient Computing for Power-Neutral Embedded Devices”, C. C. Rheinländer and N. When |
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| 13:15-14:30 |
Lunch |
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| 14:30 - 15:30 | Session 3. Voltage techniques for power reduction Session chair: A. Kakarountas S3.1 “Modelling the Reversion Loss in Switched-Capacitor DC-DC Converters with Petri Nets”, D. Li, F. Xia, J. Luo and A. Yakovlev S3.2 “Voltage Scaling and Guardband Customization of Multiple Constituent Components in SoC-FPGA”, I. Stratakos, K. Maragos and G. Lentaris S3.3 “A Calibration Procedure for Sensor Based Adaptive Voltage Scaling Approaches”, Christoph Niemann, Munawar Ali, Jakob Heller and Dirk Timmermann |
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| 15:30 – 15:45 |
Break |
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| 15:45 – 16:45 | Session 4. Approximate computing for reliability and energy optimization Session chair: A. Hatzopoulos S4.1 “Reduced Precision for Energy-Efficient Machine Learning Accelerator”, O. Elgawi S4.2 “Reliability Aspects of Approximate Adders in Industrial Wireless Communication Systems”, M. Hao, A. Najafi, A. Garcia-Oritz, L. Karsthof, S. Paul and J.Rust S4.3 “Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multipliers”, T. Cheng, J. Yu and M. Hashimoto |
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| 16:45 – 17:15 |
Break |
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| 20:00 |
Welcome Reception |
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Tuesday, July 2, 2019 |
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| 9:45 – 10:45 |
PATMOS Keynote Talk “Contactless Integrated Systems for “More than Moore” Applications”, Prof. Vasilis F. Pavlidis, Advanced Processor Technologies group, University of Manchester, UK Abstract: The idea of ubiquitous computing with 30 billion connected devices in service by 2020, ranging from micro-scale biomedical implanted chips, to portable and wearable electronics, and high performance data centres, has become an ambitious objective of this decade. Building such a diverse and complex ecosystem requires integration strategies that go beyond traditional objectives, for example, speed and area and enable new features, such as technological and functional heterogeneity, reusability, and disposability. This talk discusses a low cost, low form-factor and energy efficient integration technology where the classic wired interconnections are replaced by contactless links deployed to underpin low power applications, such as lab-on-chip systems. The advantages over the state-of-the-art, typically based on conventional wired interconnects, and the challenges for delivering these systems are described along with a methodology for the energy efficient design of these systems by exploiting heterogeneous CMOS processes. Additional considerations including cost, design tools, and modeling processes are also presented, highlighting all the diverse aspects of the ecosystem that need to be addressed towards the high volume manufacturing of contactless integrated systems. |
| 10:45 – 11:15 |
Break |
| 11:15 – 12:15 | Session 5. Design and implementation of hardware structures
Session chair: D. Soudris S5.1 “One-Hot Residue Logarithmic Number Systems”, M. Arnold, I. Kouretas, V. Paliouras and A. Morgan S5.2 “On the Static CMOS Implementation of Magnitude Comparators”, C. Efstathiou and Y. Tsiatouhas S5.3 “Radix-3 low-complexity modulo-$M$ multipliers”, I. Kouretas and V. Paliouras |
| 12:15-12:30 |
Break |
| 12:30 – 13:30 |
IOLTS Keynote Talk “From Research to Product: RAS Features in EPYC and Radeon Instinct”, Vilas Sridharan, AMD Fellow, RAS (Reliability, Availability, and Serviceability) Architecture group, AMD Abstract: The explosive growth of cloud-scale computing is a defining feature of the modern era. The datacenters that power modern clouds contain hundreds of thousands of compute nodes, each powered by highly integrated and powerful processors and compute accelerators. Provisioning adequate levels of reliability and availability for these nodes is a technical challenge, as even rare events can occur frequently at such scale. Addressing this challenge requires significant investment in research and development to understand the events that occur at scale and to design an appropriate set of features to address them. This talk will discuss reliability research conducted by AMD and describe how the results of this research affected the architecture, design, and implementation of certain reliability, availability, and serviceability (RAS) features in AMD EPYC and Radeon Instinct products. |
| 13:30 – 15:00 |
Lunch |
| 15:00 – 16:10 | Session 6. Leakage and power optimization Session chair: M. Lopez-Vallejo S6.1 “Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers”, A. Kumar and V. Kursun S6.2 “Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power”, Anala M and B. P. Harish |
| 16:30 |
Social event & Gala dinner |
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Wednesday, July 3, 2019 |
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| 9:30 – 10:30 | Poster Session B & Coffee break Session chair: G. Theodoridis B.1 “Smart sensor system for leakage detection in pipes carrying oil products in noisy environment: The ESTHISIS Project”, S. Nikolaidis, D. Porlidas, G.-O. Glentis, A. Kalfas, and C. Spandonidis B.2 “Advancing Rational Exploitation of Water Irrigation Using 5G-IoT Capabilities: The AREThOU5A Project”, A. D. Boursianis, M. S. Papadopoulou, P. Damantoulakis, A. Karampatea, P. Doanis, D. Geourgoulas, A. Skoufa, D. Valavanis, C. Apostolidis, D. G. Babas, K. B. Baltzis, T. N. Kaifas K. Siozios, S. Siskos, T. Samaras, K. Siakavara, S. Nikolaidis, S. K. Goudos, A. Liopa-Tsakalidi, P. Barouchas, I. Kasimis, G. Kalamaras, D. Merkouris, G. Perrakis, C. Tsirogiannis, A. Gotsis, K. Maliatsos B.3 “Design of a flexible multi-source energy harvesting system for autonomously powered IoT : The PERPS project”, V. Gogolou, S. Siskos, C. Tsamis, A. Kerasidou, S. Katsikas, A. Sakellariou, K. Tsiapali and G. Doumenis. |
| 10:30 – 11:30 | Session 7. Efficient architectures for neural networks
Session chair: V. Paliouras S7.1 “High Performance Accelerator for CNN Applications”, A. Kyriakos, V. Kitsakis, A. Louropoulos, E-A. Papatheofanous and D. Reisis S7.2 “Morphological Reservoir Computing Hardware”, F. Galan-Prado, J. Font and J. L. Rossello S7.3 “Stochastic Radial Basis Neural Networks”, F. Galan-Prado, A. Moran, J. Font, M. Roca and J. L Rosselló |
| 11:30-11:45 |
Break |
| 11:45 – 12:30 | Session 8. Power gating seen from a different angle
Session chair: O. Koufopavlou S8.1 “Simulation-based Verification of the Youngest-First Round-Robin Core Gating Pattern”, A. Simevski and M. Krstic S8.2 “Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design”, S. Umapathy and A. Stillmaker |
| 12:30 – 12: 45 |
Closing Remarks |
| 12:45 – 14:00 |
Lunch |
Click 
PATMOS 2019_program.pdf for the Conference program of PATMOS2019
PATMOS 2019_program.pdf for the Conference program of PATMOS2019